Performance Analysis of TCAD Based Si FinFET and Vertical GaN FinFET
Scenario 1 — Vertical GaN FinFET Scenario_1_Vertical_GaN_FinFET
Step 1: Initially, we construct a 3D Vertical GaN FinFET structure with field-plate, P-piller, and drift region design variations using proposal based parameters and customized parameters based on simulation.
Step 2: Then, we simulate Id–Vg, Id–Vd, and BV sweeps at 300 K with self-heating ON and OFF .
Step 3: Then, we detect critical device regions and apply adaptive mesh refinement to capture high-field and avalanche effects.
Step 4: Next, we perform targeted optimizations such as drift thickness/doping, field-plate geometry, and oxide selection.
Step 5: Finally, we plot performance for the following metrics:
5.1 : Gate Voltage (V) Vs Drain Current (a.u)
5.2 : Breakdown Voltage (V) Vs Fin width (u.m)
5.3 : Threshold Voltage (V) Vs Fin width (u.m)
5.4: Breakdown Voltage (V) Vs Fin Height(u.m)
5.5: Threshold Voltage (V) Vs Fin Height(u.m)
Scenario_2:Si_FinFET
Step 1: Initially, we construct a 3D Si FinFET baseline structure using proposal based parameters and customized parameters based on simulation.
Step 2: Then, we simulate Id–Vg, Id–Vd, and BV sweeps at 300 K with self-heating ON and OFF .
Step 3: Then, we detect critical device regions and apply adaptive mesh refinement to capture short-channel and fringing effects.
Step 4: Next, we perform targeted optimizations such as gate dielectric thickness, work-function tuning, and fin geometry adjustments.
Step 5: Finally, we plot performance for the following metrics:
5.1 : Gate Voltage (V) Vs Drain Current (a.u)
5.2 : Breakdown Voltage (V) Vs Fin width (u.m)
5.3 : Threshold Voltage (V) Vs Fin width (u.m)
5.4: Breakdown Voltage (V) Vs Fin Height(u.m)
5.5: Threshold Voltage (V) Vs Fin Height(u.m)
Software Requirements:
1. Development Tool: Silvaco TCAD
2. Operating System: Windows-10 (64-bit) or above
Note
1) If the plan does not meet your requirements, provide detailed steps, parameters, models, or expected results in advance. Once implemented, changes won’t be possible without prior input; otherwise, we’ll proceed as per our implementation plan.
2) If the plan satisfies your requirement, Please confirm with us.
3) Project based on Simulation only, not a real time project.
4) Please understand that any modifications made to the confirmed implementation plan will not be made after the project
doping n.type gaussian conc=6e19 characteristic=0.01 lat.char=0.1 \
peak=0.023 x.min=-2.5 x.max=-0.8
doping n.type gaussian conc=6e19 characteristic=0.01 lat.char=0.1 \
peak=0.023 x.min=2.8 x.max=4.5
doping trap acceptor e.level=1.0 concentration=1e18 gaussian peak=1 \
characteristic=0.455 degen.fac=1 sign=1e-15 sigp=1e-15
models srh print
mobility fmct.n gansat.n mup0=50
contact name=gate resistance=50*$width workfunc=5.15
contact name=drain resistance=50*$width
method climit=1e-4 ir.tol=1e-22 tol.time=1e9 dt.max=1.5625e-12 itlimit=100
output con.band charge
waveform amplitude=1.75 elec.name=gate frequency=1e10 number=1 periods=10 sinusoid
waveform amplitude=2 elec.name=gate frequency=1e10 number=2 periods=10 sinusoid
waveform amplitude=2.25 elec.name=gate frequency=1e10 number=3 periods=10 sinusoid
waveform amplitude=2.5 elec.name=gate frequency=1e10 number=4 periods=10 sinusoid
waveform amplitude=2.75 elec.name=gate frequency=1e10 number=5 periods=10 sinusoid
waveform amplitude=3 elec.name=gate frequency=1e10 number=6 periods=10 sinusoid
waveform amplitude=3.25 elec.name=gate frequency=1e10 number=7 periods=10 sinusoid
waveform amplitude=3.5 elec.name=gate frequency=1e10 number=8 periods=10 sinusoid
waveform amplitude=3.75 elec.name=gate frequency=1e10 number=9 periods=10 sinusoid
waveform amplitude=4 elec.name=gate frequency=1e10 number=10 periods=10 sinusoid
